Must Have Skills • Digital Fundamentals: Solid understanding of digital logic design and the IC design flow • Verification Methodology: Familiarity with SystemVerilog, UVM, or C++ and simulation-based verification concepts • Rigor About Correctness: Able to reason about what “correct behavior” means for a specification, and design verification that proves it rather than merely exercises it • Healthy Skepticism: Questions results that look plausible, cross-checking against the spec or an independent method before trusting them — an instinct we value regardless of prior AI exposure • Learning Agility: Curious, quick to pick up unfamiliar tools, and comfortable where methodology is still evolving • Teamwork and English: Strong collaboration, initiative to surface risks early, and sufficient English for daily communication and technical documents Preferred Education and Experience • Master’s degree or above, open to a wide range of STEM majors (electronics, microelectronics, computer science, mathematics, physics, automation, etc.) • Scripting skills (Python, Perl, Tcl) are a plus • Hands-on experience with AI coding assistants or agentic development tools is a plus • Background in AI/ML relevant to edge deployment (inference, quantization, real-time constraints, or AI hardware acceleration) is a plus • Exposure to formal verification, SVA, or coverage closure is a plus • Familiarity with AXI/AHB/APB or other bus protocols and verification IP is a plus Preferred — Shanghai • Closed-loop control systems (e.g., PID, temperature or power management) • Analog/mixed-signal co-simulation and verification methodology • System-level integration verification across multiple subsystems, or functional safety