Job Responsibilities: 1. Technical Leadership in DDR Sub-System domain (Controller and PHY) including Micro-Architecture, Design Implementation, Verification Strategy, Timing Sign-off, Integration and Silicon bring-up; 2. Responsible for the development of micro-architecture specification for GPU DDR Sub-System (Controller and PHY); 3. Responsible for the development of key design specification for block implementation; 4. Responsible for the definition of verification strategy and testplan of DDR Sub-system (Controller and PHY); 5. Responsible for Bug-Free DDR Sub-system delivery and SOC integration; 6. Technical Mentor-ship on Junior engineers in the DDR domain.     Job Requirements: 1. 10 Years+ of design or verification experience of high speed and high complexity digital logic; 2. Expertise of DDR Controller/PHY architecture and design implementation or verification, including GDDR*/HBM*/LPDDR*; 3. Successfully Tape-out and Silicon bring-up experience on advanced technology node; 4. Strong background in SV, SVA, UVM verification methodologies and C++ (for DV background); 5. Familiar with Metrics Driven Verification (MDV) or Coverage Driven Verification (CDV) Flow *(for DV background); 6. Technical leadership is required, strong interpersonal and communication skills; 7. Passion to work efficient and improvement; 8. Strong analytical/problem-solving skills, and pronounced attention to details.