Job Description: - Block/IP and SoC top level DFT implementation (MBIST, Scan, Boundary Scan, analog/IP and RF test etc.), IP/SoC DFT RTL coding and integration; - Participate in SoC CP/FT test Spec/plan definition, complete DFT Spec documents and review checklists; - SoC DFT mode SDC definition and STA support; ECO and FV check; - Test patterns/caes generation and verification, RTL/pre&post layout gate level simulation; - silicon back ATE bring-up, MP yield improvment, failure analysis and diagnosis.