1.Responsible for SOC chip-level and sub-system level DFT architecture definition, scan insertion, scan timing constraint, ATPG pattern generation/simulation, ATPG post-silicon diagnosis, MP support and etc. 2.Support chip-level/sub-system DFT related check and implementation, including ATPG DRC, ATPG coverage improve, ATPG pattern count reduction, Equivalence check, Scan SDC constraint, Timing Sign-off, Timing ECO, Power Analysis, and other scan related performance/power/area quality boost, etc. 3.Support SOC physical implementation for DFT part, and support TE for MP issue. 1.MSEE degree or above in microelectronics, computer, electronic engineering, communication engineering and other related fields 2.Familiar with Verilog and ASIC front-end design flow, with solid digital circuit theory foundation, hands-on ability and innovation ability. 3.Professional in IC front-end EDA tools (such as Sypglass/DC/PT/LEC/VCS and Tessent/DFTMAX/TMAX platforms), and with ASIC design experience, such as: RTL coding, Synthesis, P&R, STA timing signoff, IR Analysis, Post-silicon diagnosis and etc. 4.Familiar with scripting language, such as Makefile/Tcl/Perl/Python, and etc. 5.Good communication and team-work skills, good English communication and presentation experience. 6.Passion work attitude, full of curiosity about technology, courage to take responsibility, and able to work under strong pressure.