模拟/混合信号设计验证方法开发工程师当面告知
联发科技(合肥)有限公司
2027-02-08 18:32:31
社招本科硕士
岗位详情
地区:
北京市
·
合肥市
专业要求:
电子科学与技术自动化计算机科学与技术软件工程电子与计算机工程
岗位职责:
• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows.
• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.
• Document on new flows and processes for AMS DV.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or SystemC.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.
学历要求:
• BS degree and a minimum of 3 years of relevant industry experience, or
• MS degree with a minimum of 2 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field
招聘要求:
• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows.
• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.
• Document on new flows and processes for AMS DV.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips.
• Familiar with programming languages: C, C++, and/or SystemC.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.
学历要求:
• BS degree and a minimum of 3 years of relevant industry experience, or
• MS degree with a minimum of 2 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field
公司介绍

联发科技(合肥)有限公司
联发科技(合肥)有限公司,成立于2003-08-11,位于安徽,法定代表人:Hai Wang,登记状态:存续,注册资本1700万美元,公司类型:民营/私企
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公司名称:联发科技(合肥)有限公司
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